A NAND flash memory as a memory structure has an increasingly wide commercial applications, such as a smart phone, a tablet PC and a solid state disk. To fulfill requirements of these applications, the NAND flash memory is required to have low cost and high storage density. However, a conventional planar NAND flash memory is difficult to be scaled down below 20 nm because of many factors such as a limit of photolithography, short channel effects, less stored electrons and a floating gate coupling. Therefore, a three-dimensional NAND (3D-NAND) flash memory has gradually become an attention focus.
A current 3D-NAND flash memory array is classified into a gate stacked type and a channel stacked type. The gate stacked type 3D-NAND flash memory comprises a P-BiCS (Pipe-shaped Bit Cost Scalable) structure and a TCAT (Terabit Cell Array Transistor) structure. The channel stacked type 3D-NAND flash memory comprises a VG NAND (Vertical-Gate NAND) structure and a STAR (Single-Crystalline Si Stacked Array) structure.
For the gate stacked type 3D-NAND flash memory, a bit line is perpendicular to a surface of a chip, and gates are parallel with the surface of the chip and stacked in a vertical direction. With an increase of a number of stacked gate layers, a stacking of the gates is getting more and more difficult, and thus a number of the bit lines is greatly limited so that it is difficult to fulfill a 64-bit length which is predicted in ITRS (International Technology Roadmap for Semiconductors). For the channel stacked type 3D-NAND flash memory, the bit line is parallel with the surface of the chip so that a length of the bit lines is not limited. In addition, compared with the channel stacked type 3D-NAND flash memory, the gate stacked type 3D-NAND flash memory, which has disadvantages of a large unit area and a low integration level, is not applicable for a large scale memory array. Therefore, the channel stacked type 3D-NAND flash memory is more applicable for a future large scale 3D-NAND flash memory.
For a current channel stacked type 3D-NAND flash memory, only a unit in the STAR structure may use single crystal Si as a material of the channel, while a unit in the VG NAND structure may only use poly-Si as the material of the channel. For the VG NAND structure, a crystal defect and a grain interface result in a large fluctuation of a threshold voltage, a large performance difference between different memory units, a poor subthreshold characteristic and a large off-state leakage current, and thus it is difficult to obtain a uniform and stable memory unit like the unit in the STAR structure. However, because the unit in the VG NAND structure is smaller than that in the STAR structure, the VG NAND structure has advantages of a higher integration level, a simpler fabrication process, and a better process reliability. If a single crystal semiconductor is used as the material of the channel of the VG NAND structure, disadvantages of the VG NAND structure will be overcome, so that not only will the fabrication process be simplified, but also the VG NAND structure will have higher integration level so as to fulfill requirements of the future large scale 3D-NAND flash memory array.
A critical step of a method for forming the VG NAND structure with a single crystal channel lies in how to form an alternate structure of a plurality of insulating layers and a plurality of single crystal semiconductor layers. In the prior art, the alternate structure is formed by using a SiGe layer as a sacrifice layer. Specifically, an alternate structure of a plurality of SiGe layers and a plurality of single crystal Si layers is formed, then the plurality of SiGe layers are selectively etched, and then a poly crystal insulating dielectric is filled between the plurality of single crystal Si layers. This method has disadvantages of complicated steps (for example, using the SiGe layer as the sacrifice layer), high difficulty (for example, forming a floated semiconductor structure) and low yield. Moreover, overmany etchings result in an increase in crystal lattice defects in the channel and/or at interfaces, thus deteriorating a performance of a device.